The invention relates to a semiconductor device comprising a monocrystalline semiconductor body of silicon, in which at least a first region of a first conductivity type is laterally bounded by a second region comprising a countersunk first oxide layer, a highly doped silicon layer of the second opposite conductivity type disposed thereon and a second oxide layer, which is disposed thereon, is at least partly countersunk into it and extends into the first region, the side edge of the said silicon layer adjoining a highly doped contact zone of the second conductivity type, which is connected via a current path to a semiconductor zone formed in said first region which is practically bounded in projection by the edge of the second oxide layer and forms part of a semiconductor circuit element, said silicon layer being connected to a connection conductor.
The invention further relates to a method of manufacturing the device.
A semiconductor device of the kind described is known from the publication "International Electron Device Meeting" (IEDM), 1982, p. 684-687. This publication discloses a bipolar transistor structure obtained in a self-aligned manner and having very small dimensions suitable for use in highly integrated (VLSI) circuits having a high packing density. A mesa, which is enclosed by a groove and whose upper side and walls are provided with a silicon nitride layer, is then formed from an n-type conducting epitaxial layer. Subsequently, the bottom of the groove is selectively oxidized and, after the mesa wall has been exposed, a polycrystalline silicon layer is provided on the assembly. It should be noted that in the present Application the term "polycrystalline silicon layer" is to be interpreted in the widest sense as a non-monocrystalline layer and includes also, for example, an amorphous silicon layer. The said silicon layer is then limited by planarization and plasma etching to the groove. Boron is then implanted into the polycrystalline silicon and the surface of the highly doped silicon electrode thus obtained is selectively oxidized, the base contact zone being formed by diffusion from the silicon electrode. Subsequently, the upper side of the mesa is exposed and base and emitter zones are formed therein, the base zone being connected via the said base contact zone on the wall of the mesa to the wide edge of the silicon electrode.
The disadvantage of this known construction and method is inter alia that the situation at the area of the connection between the silicon base electrode and the base zone strongly depends upon the size of the so-called "bird's beak" structure, which is obtained during the selective oxidation of the silicon electrode. As will be explained more fully hereinafter, with a narrow bird's beak the transistor will locally have a thicker base zone, while possibly even the emitter base pn junction partly extends in polycrystalline silicon. Also in connection with the comparatively high base doping, this will give rise to a low emitter-base breakdown voltage and will result in a poor linearity of the transistor. On the contrary, with a very wide bird's beak, the situation may arise that the connection between the base contact zone and the base zone is interrupted.
Further, in connection with the manufacturing method used, the upper side of the silicon electrode in this known device will always be located at a lower level than the upper surface of the mesa. In order to obtain a reasonable contact surface between the silicon electrode and the base contact zone, this connection must have a height of at least about 0.6 .mu.m. For this purpose, the groove must be comparatively deep and the polycrystalline silicon layer must be comparatively thick.
The invention has inter alia for its object to provide an improved structure of a semiconductor device of the kind described, in which the connection with the side edge of the silicon electrode can be established in a reproducible manner and independently of the form of the bird's beak, as a result of which inter alia bipolar transistors having a high efficiency and very small dimensions can be obtained, which have a stable emitter-base junction and a good linearity. The invention can also be used in semiconductor devices other than bipolar transistors, for example MOS transistors, and further relates to a method of manufacturing such a device.
The invention is based inter alia on the recognition of the fact that the result aimed at can be obtained in that the connection with the side edge of the electrode is combined in a suitable manner with a zone or interstice, whose location and dimension can be fully determined in a self-aligned manner.
According to the invention, a semiconductor device of the general kind described above is characterized in that the upper side of the silicon layer is located at a higher level than the surface of the first region and in that the contact zone is connected to the said semiconductor zone via an intermediate region located in the first region at least in part below the second oxide layer and having a lower doping concentration than the contact zone.
Due to the fact that in the semiconductor device according to the invention the contact zone is connected not directly, but through an intermediate region, to the semiconductor zone of the second conductivity type forming part of the semiconductor circuit element, which intermediate region can be formed independently of the bird's beak forming part of the second oxide layer, the said problems caused by the bird's beak do not occur in a device according to the invention.
The invention further relates to a method of manufacturing the device, which method is characterized in that
(a) a first anti-oxidation layer is provided on the surface of a silicon region of a first conductivity type,
(b) a first layer of a first material is provided on the first anti-oxidation layer,
(c) a pattern is formed from the first layer,
(d) edge portions of a second material selectively etchable with respect to the first material are provided along the circumference of the first layer,
(e) the uncovered part of the first anti-oxidation layer is removed,
(f) a depression is etched into the exposed part of the silicon region,
(g) a further anti-oxidation layer is provided on the assembly,
(h) the further anti-oxidation layer is removed by plasma etching from all the surfaces parallel to the surface,
(i) the silicon surfaces not covered by the further antioxidation layer are provided by thermal oxidation with a first oxide layer,
(j) after the further anti-oxidation layer has been removed, the depression is filled by deposition and planarization with a highly doped silicon layer of the second conductivity type up to a level above the surface of the silicon region
(k) the edge portions are removed by selective etching,
(l) an intermediate region is formed in the silicon located below the edge portions by introduction of a dopant,
(m) the exposed part of the first anti-oxidation layer is removed,
(n) the first layer of the first material is removed by selective etching, and
(o) the exposed silicon is provided by thermal oxidation with a second oxide layer, a contact zone of the second conductivity type being formed in the silicon region by diffusion from the highly doped silicon layer of the second conductivity type.